Use an x86 segment register instead of a GPR for the Intel processor register


This issue replaces the SF RFE tracker 1147081:

Some papers describe using segment registers to free a register. For example, in "Evolution of a java just-in-time compiler for IA-32 platforms" by T. Suganuma, T. Ogasawara, K. Kawachiya, M. Takeuchi, K. Ishizaki, A. Koseki, T. Inagaki, T. Yasue, M. Kawahito, T. Onodera, H. Komatsu and T. Nakatani, FS is described as being used to access thread local storage (TLS). Its not clear this is worth while as although the hardware allows access to different segment registers Intel state in some manuals that they will only rename 2, and using more than 2 incurs a penalty. This doesn't really make sense to me as typically CS, DS and SS are all different segment due to memory protection. Also GS is used in Linux to provide TLS.

In the sourceforge tracker I demonstrated some GCC magic that could be used to calculate offsets for TLS by hijacking the underlying TLS support of GCC. Namely:

#include <stdio.h>
static __thread char *hello;
int main(int argc, char **argv) {
int offset;
asm ("mov $hello@NTPOFF, %0" : "=r"(offset));
hello = "hello";
printf("%p %s %d",&hello, hello, offset);

where the asm mov is pulling the TLS offset for us so that we could use it inside our compilers.

There's a lot more discussion of this on the SF tracker and its still not clear whether making the change is worthwhile.






Ian Rogers



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